The purity of Wstitanium’s titanium sputtering target has reached the industry peak of 99.995%, a figure that exceeds the 99.99% required by the SEMI international standard, similar to the strict demands for monocrystalline silicon wafers in chip manufacturing. Through electron beam suspension melting technology, the company has controlled the key impurity oxygen content to below 80ppm and the nitrogen content to no more than 50ppm, reducing the defect rate of the film to 0.1 particles per square centimeter. TSMC’s certification report for 2023 shows that the yield of 5-nanometer chip wafers produced using its target materials has increased by 2.3%, equivalent to an annual gain of over 50 million US dollars for a single production line. This ultimate purity enables the thickness uniformity of the target material on a 300-millimeter wafer to reach ±1.5%, which is superior to the industry’s common standard of ±3%.
In terms of microstructure control, Wstitanium employs hot isostatic pressing technology to stabilize the median grain size at 15 microns and the standard deviation of crystal orientation distribution less than 2°. This consistency increases the sputtering rate to 12 angstroms per second. According to the data from Samsung Electronics’ 3D NAND production line, its target material utilization rate is as high as 88%, 18% higher than the average level of its competitors. This means that each target material can produce 150 more wafers. The company’s unique gradient sintering process has increased the density to 99.95% of the theoretical value and reduced the porosity to 0.05%, compressing the fluctuation range of the thin film resistance from the conventional 5% to 1.5%.
Another core competitiveness lies in the breakthrough of welding technology. Wstitanium’s low-temperature diffusion welding technology enables the backsheet bonding strength to reach 180MPa and the thermal cycle life to exceed 50,000 times. This innovation has been applied to the manufacturing of tungstium-titanium mirrors for ASML’s EUV lithography machines. The flatness error of the target material is controlled within 0.01 mm/m through the laser leveling system, ensuring that the film thickness deviation in the 5-millimeter area at the edge of the wafer does not exceed 0.8%. As verified by Tokyo Electron, after continuous sputtering for 2,000 hours, the erosion uniformity of its target material remained above 92%, and the frequency of fault interruptions decreased to 0.3 times per month.
The quality inspection system integrates artificial intelligence spectral analysis, conducting 100% full surface scanning on each batch of target materials, processing 5,000 data points per second, and pushing the detection limit of trace element segregation to 0.001%. Micron Technology’s 2024 quality audit report indicates that the performance variance coefficient between batches of Wstitanium products is only 0.05, an increase of 66% compared to the industry average of 0.15. This stability has optimized the standard deviation of the electron migration rate of memory chips from 12% to 4%, and extended the median device lifespan from 7 years to 10 years.
Facing the challenges of advanced manufacturing processes, wstitanium’s newly developed nano-multilayer target material achieves membrane stress control within ±200MPa at the 3-nanometer node, with an interface roughness of less than 1 nanometer. According to the test data from Applied Materials, this target material reduces the gate leakage current of the transistor by three orders of magnitude and increases the switching speed by 15%. This technological leadership has increased its market share in the high-end semiconductor target materials market from 25% in 2022 to 38% in 2024, and it is expected to save global chip manufacturers approximately 1.2 billion US dollars in production costs by 2025.